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AVS Technology
FEATURES
* Complete DAC and ADC Audio CODEC with headphone driver. * Up to 96kHz input sampling frequencies for ADC/DAC * Selectable DAC De-emphasis Filter. * Selectable ADC High Pass Filter * Programmable Audio Data Interface * I2S, Normal, Left justified or DSP data for ADC/DAC * 16,18, 20 and 24-bit input data resolution * System clock: 64fs, 96fs,128fs, 192fs, 256fs or 384fs * 250fs and 272fs system clock for USB application * Master or Slave Clocking mode * Regular audio or USB mode audio * 2 or 3-wire software control interface selectable by external pin. * 2 channel microphone or line inputs * Programmable power down features to conserve power
AV2722
AUDIO CODEC WITH HEADPHONE DRIVER AND PROGRAMMABLE SAMPLE RATES
DESCRIPTION
The AV2722 is a mixed signal CMOS monolithic device which is a low cost audio CODEC designed with a built-in headphone driver. It supports regular audio or USB mode audio and is therefore ideal for portable MP3 audio and speech players and recorders. It can also be used for minidisk, CD-RW machines. Stereo line audio inputs with programmable gain are provided A microphone bias voltage output is also provided which makes the AV2722 ideal for an electret type microphone. For the multi-bit signal delta DAC, 64X oversampling digital interpolation filter is used with programmable de-emphasis, volume control, and sampling rate selection features. The DAC supports I2S, Normal, Left justified or DSP data with 16, 18, 20 and 24-bit resolution. Sampling rates from 8KHz to 192 KHz are supported. At the DAC output, stereo headphone drivers are built in for driving headphones. For the multi-bit delta-sigma ADC, programmable gain are provided at the input. state of the art decimation filter is used to down-sample the received signal and finally a selectable high pass filter is used to reduce un-wanted low frequency noise. The digital audio serial output can be programmed at various formats similar to the DAC input.
GENERAL
* 2.7-volt to 3.6-volt Power Supply range (TBD) * 28-pin SSOP package
APPLICATIONS
* Low cost, CD-quality consumer audio equipment * Portable MP3 Players and Recorders ADVANCE PRODUCT INFORMATION. AVS RESERVES THE RIGHT TO MODIFY THIS PRODUCT WITHOUT NOTICE.
XCK
VDD
VDDH
VDDA
D R
A FT
LOW PASS FILTER LOW PASS FILTER HEADPHONE DRIVER HEADPHONE DRIVER GAIN CONTROL GAIN CONTROL
CLOCK GENERATOR
HPDET AOUTL HOUTL AOUTR HOUTR VCM HPVR AINL AINR MICBIAS
AUDIO
DIGITAL AUDIO I/O INTERFACE
SDI SFDA
SERIAL INPUT PORT
INTERPOLATION DIGITAL FILTER
MULTI-LEVEL DELTA-SIGMA MODULATOR
DAC
DAC
SC SFAD
VOLUME CONTROL AUDIO SERIAL OUTPUT PORT HIGH PASS FILTER DECIMATION DIGITAL FILTER MULTI-LEVEL DELTA-SIGMA MODULATOR ADC ADC
SDO
2 OR 3 WIRE SERIAL COMMAND PORT
SDA SCL
CSB
MODE
RS/
VSS
VSSH
VSSA
VSSA
AV2722 BLOCK DIAGRAM
AVS Technology Inc. 4110 Clipper Ct., Fremont CA94538 Tel: (510) 353-0848 Fax: (510) 353-0856
1-29
January 22, 2004
AV2722 (Preliminary)
PIN CONFIGURATION
VDD SC SDI SFDA SDO SFAD HPVR VDDH HOUTL HOUTR VSSH AOUTL AOUTR VDDA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 AV2722
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VSS XCK RS/ SCL SDA CSB MODE HPDET AINL AINR MICBIAS VCM VSSA VSSA
ORDERING INFORMATION
PRODUCT AV2722
PACKAGE 28-pin SSOP
TEMPERATURE RANGE -25 TO +85oC
2-29
January 22, 2004
AV2722 (Preliminary)
PIN ASSIGNMENTS
Pin No. Pin Name 1 2 3 4 VDD SC SDI SFDA Supply
Type
Description Power supply for digital circuits DAC serial input data bit clock. It is input for slave mode and output for master mode. DAC serial input data. It can be in normal, left justified, i2s, or DSP type DAC sample rate clock. It is input for slave mode and output for master mode. For normal or left-justified type SDI data input, a high in SFDA indicates left channel data, a low in SFDA indicates right channel data. For I2S type, a low in SFDA indicates left channel data, a high in SFDA indicates right channel data.For DSP mode, a"sync" pulse in SFDA is followed by two data words, left channel data is followed by right channel data. ADC serial output data. It can be in normal, left justified, i2s, or DSP type. ADC sample rate clock. It is input for slave mode and output for master mode. For normal or left-justified type SDO data output, a high in SFAD indicates left channel data, a low in SFAD indicates right channel data. For I2S type, a low in SFAD indicates left channel data, a high in SFAD indicates right channel data. For DSP mode, a"sync" pulse in SFAD is followed by two data words, left channel data is followed by right channel data. Voltage reference for CAPLESS headphone connection.. Power supply for headphone circuits. Left channel headphone output. Right channel headphone output. Ground for headphone circuits. Left channel audio line output. Right channel audio line output. Power supply for analog circuits. Ground for analog circuits. Ground for analog circuits Analog circuits common mode reference. Microphone bias. Right channel line/microphone input.
Digital Input/Output Digital Input Digital Input/Output
5 6
SDO SFAD
Digital Output Digital Input/Output
7 8 9 10 11 12 13 14 15 16 17 18 19
HPVR VDDH HOUTL HOUTR VSSH AOUTL AOUTR VDDA VSSA VSSA VCM MICBIAS AINR
Analog Output Supply Analog Output Analog Output Ground Analog Output Analog Output Supply Ground Ground Analog output Analog Output Analog Input
3-29
January 22, 2004
AV2722 (Preliminary)
Pin No. Pin Name 20 21 AINL HPDET Type Analog Input Digital Input Description Left channel line/microphone input Headphone is plugged in or not plugged in indicator. The polarity of this signal can be inverted or not inverted, which is controlled by programming bit HPDETMODE (creg4[2], address 04 hex), a logic "low" inverts the polarity of HPDET into the chip. I2C or MPU control interface selection. If MODE is logic "high", the chip is using MPU for chip programming. If MODE is logic "low", the chip is using I2C for chip programming. MODE can be no-connect for MPU control due to the internal "pullup" resistor. 3-wire MPU chip select, active low. 3-wire MPU data input /output or 2-wire I2C data input/output 3-wire MPU clock input /2-wire I2C clock input Active low chip reset Chip clock input. The clock rate of XCK depends on the audio sampling rate, regular audio or USB audio. Ground for digital circuits
22
MODE
Digital Input
23 24 25 26 27 28
CSB SDA SCL RS/ XCK VSS
Digital Input Digital Input/Output Digital Input Digital Input Digital Input Ground
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuits is manufactured on a CMOS process. It can be damaged by ESD. AVS recommends that all integrated circuits be handled with appropriate ESD precautions. Improper handling and installation procedures can cause damage to the device.
4-29
January 22, 2004
AV2722 (Preliminary)
XCK SYSTEN CLOCK REQUIREMENT The system clock (XCK at pin 27) for the AV2722 supports audio sampling rates from 64fs to 384fs for regular type audio, where fs is the audio sampling frequency (SFDA /SFAD), typically 8KHz, 44.1KHz, 48KHz, 96KHz, or 192KHz. For USB type audio, SFDA /SFAD is either 250fs or 272fs. XCK is used to operate the digital interpolation filter and the delta-sigma modulator. By using the two-wire (I2S) or 3-wire (MPU type) serial command port, user can program the chip to accept different clock frequency under different sampling rate.
Sampling Rate
XCK Clock Frequency (MHz) For Regular Mode 64fs N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 12.288 96fs N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 18.432 128fs N/A N/A N/A N/A N/A N/A N/A N/A 11.289 12.288 24.576 192fs N/A N/A N/A N/A N/A N/A N/A N/A 16.934 18.432 36.864 256fs 12.288 12.288 12.288 12.288 11.289 11.289 11.289 11.289 N/A N/A 49.152 384fs 18.432 18.432 18.432 18.432 16.934 16.934 16.934 16.934 N/A N/A 73.728
ADC
48KHz 48KHz 8KHz 8KHz 44.1KHz 44.1KHz 8KHz 8KHz 88.2KHz 96KHz OFF
DAC
48KHz 8KHz 48KHz 8KHz 44.1KHz 8KHz 44.1KHz 8KHz 88.2Khz 96KHz 192KHz
Sampling Rate
XCK Clock Frequency (MHz) For USB Mode 250fs 12 12 12 12 12 N/A N/A N/A N/A N/A N/A 272fs N/A N/A N/A N/A N/A 12 12 12 12 12 12
ADC
48KHz 48KHz 8KHz 8KHz 96KHz 44.1KHz 44.1KHz 44.1KHz 8KHz 8KHz 88.2KHz
DAC
48KHz 8KHz 48KHz 8KHz 96KHz 44.1KHz 8KHz 8KHz 44.1KHz 8KHz 88.2KHz
5-29
January 22, 2004
AV2722 (Preliminary)
MASTER AND SLAVE MODE OPERATION - DIGITAL AUDIO INTERFACE The AV2722 can be operated in either master or slave mode. By default, the chip is set to operate in "Slave" mode. To configure the chip for "Master" mode operation, the programming bit MASTER (CREG6[7]) must be programmed to "1". In master mode operation, AV2722 acts as a master which generates SC, SFAD, and SFDA. In slave mode operation, AV2722 receives these signals from an audio DSP encoder/decoder source.
SC SFDA
AV2722
SFAD SDI SDO
AUDIO DSP PROCESSOR
AV2722 in Master Mode
SFDA (PIN 4) OR SFAD (PIN 6)
tmsfd
SC (PIN 2)
SDI (pin 3)
tmSU tmsdod tmHD
SDO (pin 5)
SDI audio data setup time SDI audio data hold time SFDA/SFAD propagation delay from SC SDO propagation delay from SC
tmSU tmHD tmsfd tmsdod
10 ns (min) 10 ns (min) 10 ns (max) 10 ns (max)
Audio Data Input Timing - MASTER MODE
6-29
January 22, 2004
AV2722 (Preliminary)
SC SFDA
AV2722
SFAD SDI SDO
AUDIO DSP PROCESSOR
AV2722 in Slave Mode
SFDA (PIN 4) OR SFAD (PIN 6)
tscH tsc tscsf tsfsc
SC (PIN 2)
tscL
SDI (pin 3)
tS U tH D
SDO (pin 5)
SC pulse cycle time SC pulse width, High SC pulse width, Low SDI audio data setup time SDI audio data hold time SC to SFDA / SFAD edge
tsc tscH tscL tS U tH D
tscsf tsfsc
50 ns (min) 20 ns 20 ns 10 ns 10 ns 10 ns 10 ns 10 ns (min) (min) (min) (min) (min) (min) (max)
SFDA / SFAD edge to SC SDO propagation delay from SC
tsdod
Audio Data Input Timing - SLAVE MODE
7-29
January 22, 2004
AV2722 (Preliminary)
I2S MODE In I2S Mode, the MSB of the audio data SDI is sampled on the second rising edge of SC following SFDA/SFAD transition. SFDA/SFAD are low during the left channel samples and high during the right channel samples.
1/fs Left channel
SFDA (PIN 4) OR SFAD (PIN 6)
Right channel
SC (PIN 2)
SDI (PIN 3) (16-BIT AUDIO DATA) SDI (PIN 3) (18-BIT AUDIO DATA) SDI (PIN 3) (20-BIT AUDIO DATA) SDI (PIN 3) (24-BIT AUDIO DATA)
15 MSB 17 MSB 19 MSB 23 MSB
14
2
1
0 LSB
15 MSB 0 LSB 17 MSB 0 LSB 19 MSB 0 LSB 23 MSB
14
2
1
0 LSB
16
2
1
16
2
1
0 LSB
18
2
1
18
2
1
0 LSB
22
21
2
1
22
21
2
1
0 LSB
"I 2 S" Data Input Timing
Normal Mode In Normal Mode, the audio data, SDI, is right-justified. The LSB are aligned with the rising/falling edge of SFDA/ SFAD. Data is latched into the chip on the rising edge of SC. SFDA/SFAD are high during the left channel samples and low during the right channel samples.
1/fs SFDA (PIN4) OR SFAD (PIN 6) Right channel
Left channel
SC (PIN 2)
SDI (PIN3)
2
1
0
15 MSB
14
2
1
0 LSB
15 MSB 17 MSB 19 MSB 23 MSB 22 21 18 16
14
2
1
0 LSB
(16-BIT AUDIO DATA) SDI (PIN3)
2
1
0
17 MSB
16
2
1
0 LSB
2
1
0 LSB
(18-BIT AUDIO DATA) SDI (PIN3)
2
1
0
19 MSB
18
2
1
0 LSB
2
1
0 LSB
(20-BIT AUDIO DATA) SDI (PIN3)
2
1
0
23 MSB
22
21
2
1
0 LSB
2
1
0 LSB
(24-BIT AUDIO DATA)
"Normal" Data Input Timing
8-29
January 22, 2004
AV2722 (Preliminary)
LEFT JUSTIFIED MODE In Left Justified mode, the MSB of the audio data SDI is sampled on the first rising edge of SC following SFDA/ SFAD transition. SFDA/SFAD are high during the left channel samples and low during the right channel samples.
1/fs
SFDA (PIN 4) OR SFAD (PIN 6)
Left channel
Right channel
SC (PIN 2)
SDI (PIN 3) (16-BIT AUDIO DATA) SDI (PIN 3) (18-BIT AUDIO DATA) SDI (PIN 3) (20-BIT AUDIO DATA) SDI (PIN 3) (24-BIT AUDIO DATA)
15 MSB 17 MSB 19 MSB 23 MSB
14
2
1
0 LSB
15 MSB 0 LSB 17 MSB 0 LSB 19 MSB 0 LSB 23 MSB
14
2
1
0 LSB
16
2
1
16
2
1
0 LSB
18
2
1
18
2
1
0 LSB
22
21
2
1
22
21
2
1
0 LSB
"Left Justified" Data Input Timing
DSP Mode In DSP Mode, the audio data SD is in time division multiplexed format. The left and right channel data are shifted into the chip in sequence with the left channel data first followed by the right channel data. SFDA/SFAD is a "sync" pulse which appears every 1/fs time. The minimum SFDA/SFAD sync-pulse is one SC cycle.
SFDA (PIN 4) OR SFAD (PIN6)
1/fs
1 SC
SC (PIN 2)
SDI (PIN3) (16-BIT AUDIO DATA)
15 MSB 17 MSB 19 MSB
14
2 Left channel
1
0
15
14
2 Right channel
1
0 LSB 2 1 0 LSB 2 1 0 LSB
15
LSB MSB 2 1 0 LSB 2 1 17 MSB 0
No valid data
17
SDI (PIN3) (18-BIT AUDIO DATA)
16 Left channel 18 Left channel
16 Right channel 19 18
No valid data
19
SDI (PIN3) (20-BIT AUDIO DATA)
LSB MSB
Right channel
No valid data
1 0 LSB
SDI (PIN3) (24-BIT AUDIO DATA)
23 MSB
22
21 Left channel
2
1
0 LSB
23 MSB
22
21 Right channel
2
23
No valid data
DSP Mode Timing
9-29
January 22, 2004
AV2722 (Preliminary)
SOFTWARE CONTROL INTERFACE The AV2722 programmable registers can be programmed via the software control interface. Either 3-wire (MPU type) or 2-wire (I2S) interface are supported. The MODE pin sets the selection of the software control interface.
MODE (PIN No. 22) 0 1
SOFTWARE CONTROL INTERFACE 2-wire I2S 3-wire MPU type
3-WIRE SERIAL COMMAND PORT By default, the AV2722 is set to use the 3-wire, microprocessor-type interface (MPU). Because MODE pin is internally pulled up to default the chip in MPU programming mode. Therefore, the MODE pin can be "no-connect" if MPU interface is used. The 3-wire serial command port receives serial input data (SDA), serial input clock (SCL) and active low chip select (CSB). The serial data is clocked in by the rising edge of the serial input clock if CSB is low. The 16 bit serial input data contains 8 address control bits followed by 8 data bits. The address control bits are: D[15:14] - chip ID. (For the AV2722, chip ID is binary "10") D[13] - read/write control bit. (For the AV2722, D[13]=1 for read and 0 for write) D[12:8] - 5-bit programmable register address. The data bits are:D[7:0] - 8 bit data. An example is given to write into address `00010' with data `0000_0100'.
CSB
D15 D14 D13 D12 D11 D10 D9
SDA SCL CHIP ID R/W 5-BIT ADDRESS
1 0 0 0 0 0 1
D8
0
D7
0
D6
0
D5
0
D4
0
D3
0
D2
1
D1
0
D0
0
D15 D14
8-BIT DATA
CHIP ID
Chip ID, D[15:14] =10 Read /Write D[13] = 0 for write Address, [12:8] = 00010 Data, D[7:0] = 0000_0100
3-Wire MPU- type Serial Control Port Timing Diagram
10-29
January 22, 2004
AV2722 (Preliminary)
t csbl
CSB (PIN23)
t csbh
TSCL t SCLH
SCL (PIN 25)
tsclcsb tcsbscl
t SCLL
SDA (PIN24)
t sdasu
t sdahd
3-Wire MPU-type Serial Control Port Timing Requirement
11-29
January 22, 2004
AV2722 (Preliminary)
2-WIRE (I2C) SERIAL COMMAND PORT The AV2722 also provides a 2-wire I2C Serial Command Port for chip programming. User can use this port to program the internal control registers. The Chip Address for the AV2722 is a 7-bit hexadecimal number "32hex". The protocol for write operation consists of sending 3 bytes of data to the AV2722 at the SDA pin. Following each byte is the acknowledge generated by the AV2722. The first byte is the 7-bit Chip Address followed by the read/ write bit (read is logic "high" and write is logic "low") The second byte is the AV2722 control register address. The third byte is the control register data. An example which illustrates "write" timing of register address 00H and data 30H is given below.
START CA6 SDA
0 1 1 0 0 1
CA0 R/W ACK A7
0
A6
A5
A4
A3
A2
A1
A0 ACK D7
D6
D5
D4
D3
D2
D1
D0 ACK
STOP
SCL
Chip Address: CA[6:0]=011_0010 Register Address: A[7:0]= 00H Data: d[7:0] = 30H
I2S - Serial Command Port Timing Diagram
t BUF
SDA
t HD;STA
t HIGH
t SU;DAT
t SU,STA
t HD; STA
tr t SU,STO
SCL P
S
t LOW tr tf
Sr
t HD;DAT
P
I2S - Serial Command Port Timing Requirement
To use the 2-wire I2C serial command port, the MODE pin must be connected to ground through a pulldown resistor. Upon power up, all programming registers are set to default values. By default, or without using I2C or MPU-type port, the AV2722 is set ready to run 256fs clock frequency with 44.1K or 48K sampling rate, and to accept 24-bit, Ieft justitied data, with de-emphasis filtering turns off.
12-29
January 22, 2004
AV2722 (Preliminary)
REGULAR OR USB AUDIO DATA The AV2722 can be operated in regular (non-USB) or USB (Universal Serial Bus) modes. The usage of regular or USB applications are programmed via the 3-wire or 2-wire serial command port. The selection of sampling rates for regular or USB modes are controlled by CREG3[7:0]. Please refer to the section "Programmable Control Register Assignment" below. In regular audio application, the user selects an appropriate XCK clock which is generated by an off chip oscillator.The user then program the chip for desired ADC, DAC sampling frequencies. By default, the chip is set to operated at 48KHz sampling rate, 256fs for both the ADC and DAC, with XCK running at 12.288 MHz. The AV2722 supports sampling rates from 8KHz to 96 KHz for both ADC and DAC. For 192 KHz sampling rate, only the DAC path is operational. The ADC path is "turned off". In USB system, the common USB clock frequency is 12 MHz. To use the AV2722 for USB application, XCK should be running at 12 MHz. PROGRAMMABLE CONTROL REGISTER ASSIGNMENT The are 13 Programmable Registers in the AV2722. The function and address assignment of these registers are described in the following table. All these programmable registers can be read back via the Serial Command Port.
Address (7-bit hex) 0 1 2 3 4 5 6 7 8 9 A B C
Register VOLREG[7:0] CREG1[7:0] CREG2[7:0] CREG3[7:0] CREG4[7:0] CREG5[7:0] CREG6[7:0] CREG7[7:0] CREG8[7:0] CREG9[7:0] CREG10[7:0] CREG11[7:0] CREG12[7:0]
Default Value (hex) 7F 00 00 00 00 40 00 03 12 12 06 00 00
Register Function Volume value for both left and right channel De-emphasis control DAC path serial input port control DAC, ADC sampling frequency selection control DAC and miscellaneous power down control DAC headphone control ADC path serial output port control ADC high-pass filter control ADC path left channel gain and mute control ADC path right channel gain and mute control ADC power down control ADC path left and right microphone gain control Chip software reset
13-29
January 22, 2004
AV2722 (Preliminary)
ADDRESS 00, VOLUME REGISTER (CREG0[7:0]) CREG0[7:0] A[7:0] BIT7 Hex 00 Default Value 0 1 1 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 VOLUME[7:0] 1 1 1 1 1
VOLUME[7:0]: control the volume of the left and right DAC channels concurrently. Default value is 8'h7F. ADDRESS 01, DE-EMPHASIS CONTROL REGISTER (CREG1[7:0]) CREG1[7:0] A[7:0] BIT7 Hex 01 Default Value 0 0 0 BIT6 BIT5 BIT4 Reserved 0 0 0 0 BIT3 BIT2 BIT1 BIT0
DEEMP
0
DEEMP:De-emphasis Control 0: by-pass the de-emphasis filter in the DAC path (default). 1: enable the de-emphasis filter in the DAC path. ADDRESS 02, DAC PATH SERIAL INPUT PORT CONTROL REGISTER (CREG2[7:0]) CREG2[7:0] A[7:0] BIT7 Hex 02 Default Value bpf48 0 BIT6 dahrsc 0 BIT5
dasfdly
BIT4
dainvsc
BIT3
BIT2
BIT1
BIT0
damode[1:0] 0 0
daformat[1:0] 0 0
0
0
BPF48: Bit per SFDA/SFAD frame control
0: bit per frame is 64 bit, i.e. 32-bit for the left channel and 32-bit for the right channel for the SD input and SDO output. 1:bit per frame is 48 bit, i.e. 24-bit for the left channel and 24-bit for the right channel for the SD input and SDO output.
DAHRSC: DACs use higher rate SC
0: DAC path uses whatever SC is provided, either master or slave mode (default). 1: DAC path uses higher rate SC. When the ADC path is at higher sampling than the DAC path, program this bit to "1" allows SD input to come in at the higher SC rate.
DASFDLY: Delay SFDA by 1 SC in the DAC path.
0: do not delay the SFDA by 1 SC cycle (default). 1: delay the SFDA by 1 SC cycle.
DAINVSC: Invert the SC bit clock.
0: do not invert the SC bit clock (default). 1: invert the SC bit clock.
14-29
January 22, 2004
AV2722 (Preliminary)
DAMODE[1:0]: These two bits define the DAC path serial data input mode.
00: left justified mode (default). 01: I2S mode. 10: normal mode 11: DSP mode
DAFORMAT[1:0]: These two bits define the audio serial input data bit length.
00: 24 bits (default). 01: 20-bits. 10: 18 bits. 11: 16 bits.
ADDRESS 03, DAC, ADC SAMPLING FREQUENCY SELECTION CONTROL REGISTER (CREG3[7:0]) CREG3[7:0] A[7:0] BIT7 Hex 03 Default Value 0 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 Reserved 0 0 0
freqcon[5:0]
0
0
0
0
The freqcon[5:0] are used to set up the device to work under different XCK clock rate and various sampling rate combinations. The following table defines programming values under different XCK and sampling rate conditions.There are 26 various cases for regular (non-USB) mode and 10 various cases for USB mode.
15-29
January 22, 2004
AV2722 (Preliminary)
Regular (non-USB) Mode Frequency Control Register Settings SAMPLING RATE ADC KHz
48 48 48 48 8 8 8 8 44.1 44.1 44.1 44.1 8 8 8 8 88.2 88.2 96 96 OFF OFF OFF OFF OFF OFF
DAC KHz
48 48 8 8 48 48 8 8 44.1 44.1 8 8 44.1 44.1 8 8 88.2 88.2 96 96 192 192 192 192 192 192
XCK FREQUENCY MHz
12.288 18.432 12.288 18.432 12.288 18.432 12.288 18.432 11.289 16.934 11.289 16.934 11.289 16.934 11.289 16.934 11.289 16.934 12.288 18.432 12.288 18.432 24.576 36.864 49.152 73.728
SFDA SFAD NO. OF XCK
256 384 256 384 256 384 256 384 256 384 256 384 256 384 256 384 128 192 128 192 64 96 128 192 256 384
FREQUENCY CONTROL REGISTER PROGRAMMING VALUES FREQCON[5:0] No.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
BIT5
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1
BIT3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1
BIT2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0
BIT1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
BIT0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
16-29
January 22, 2004
AV2722 (Preliminary)
USB Mode Frequency Control Register Settings SAMPLING RATE ADC KHz
48 48 8 8 96 44.1 44.1 8 8 88.2
DAC KHz
48 8 48 8 96 44.1 8 44.1 8 88.2
XCK FREQUENCY MHz
12 12 12 12 12 12 12 12 12 12
SFDA SFAD NO. OF XCK
250 250 250 250 250 272 272 272 272 272
FREQUENCY CONTROL REGISTER PROGRAMMING VALUES FREQCON[5:0] No.
32 33 34 35 36 37 38 39 40 41
BIT5
1 1 1 1 1 1 1 1 1 1
BIT4
0 0 0 0 0 0 0 0 0 0
BIT3
0 0 0 0 0 0 0 0 1 1
BIT2
0 0 0 0 1 1 1 1 0 0
BIT1
0 0 1 1 0 0 1 1 0 0
BIT0
0 1 0 1 0 1 0 1 0 1
ADDRESS 04, DAC AND MISCELLANEOUS POWER DOWN CONTROL REGISTER (CREG4[7:0]) CREG4[7:0] A[7:0] BIT7 Hex 04 Default Value
Reserved
BIT6
pwdnpullupr
BIT5
pwdncapless
BIT4
pwdnvcm
BIT3
pwdnline
BIT2
hpdetmode
BIT1
capless
BIT0
mute
0
0
0
0
0
0
0
0
PWDNPULLUPR: Power down pullup resistor at the MODE pin.
0: turn on the pullup resistor at the MODE pin (default). 1:disable the pullup resistor at the MODE pin. This bit is used to reduce power consumption in the pullup resistor at the MODE pin if user uses I2C for chip programming. For I2C, the chip needs an external pulldown resistor at the MODE pin. User can program this bit to "1" to disable the internal pullup resistor. For user using the 3-wire MPU interface, the external pullup resistor is not needed. By default, the chip is in MPU mode with the internal pullup resistor enabled.
PWDNCAPLESS: Power down the analog "capless" circuit block.
0: do not power down the analog "capless" circuit block (default). 1: power down the "analog "capless" circuit block.
17-29
January 22, 2004
AV2722 (Preliminary)
This bit must be used together with "CAPLESS" (CREG4[1]) for headphone output application. If user is using external coupling capacitors at headphone output pins HPOUTL and HPOUTR, CAPLESS should be programmed to "1" (CAPLESS circuit block is not used), PWDNCAPLESS should be programmed to "1" to conserve power consumption.
PWDNVCM:Power down the resistor at the analog common mode voltage reference.
0: do not power down the resistor at the analog common mode voltage reference(default). 1: power down the resistor at the analog common mode voltage reference.
PWDNLINE:Power down the line outputs simultaneously.
0: do not power down the line outputs (default). 1: power down the line outputs simultaneously. When headphone is used, this bit must be programmed to "1" to conserve power consumption.
HPDETMODE:Headphone detection mode.
0: invert the HPDET pin signal inside the chip (default). 1: do not invert the HPDET pin signal inside the chip. This bit provides the flexibility to invert or not invert the HPDET pin signal inside the chip.
CAPLESS: External coupling capacitor of headphone is used or not used at HPOUTL and HPOUTR.
0: external coupling capacitor is not used, the chip internal "capless" circuit block is needed (default). 1: external coupling capacitor is used, the chip internal "capless" circuit block is not needed. This bit must be programmed together with PWDNCAPLESS (CREG4[5]). By default, external coupling capacitor at headphone outputs are not used. If they are used, both CAPLESS and PWDNCAPLESS must be programmed to "1" to conserve power consumption
MUTE: Mute the DAC AOUTL and AOUTR outputs
0: do not mute the DAC AOUTL and AOUTR outputs (default). 1: mute the DAC AOUTL and AOUTR outputs, the headphone HPOUTL and HPOUTR are not "muted".
.ADDRESS 05, DAC PATH HEADPHONE CONTROL REGISTER (CREG5[7:0])
CREG5[7:0] A[7:0] BIT7 Hex 05 Default Value
Reserved
BIT6
BIT5
BIT4
BIT3 hpagcd[6:0]
BIT2
BIT1
BIT0
0
1
0
0
0
0
0
0
HPAGCD[6:0]: 7-bit headphone automatic gain control AGC data. Default value of HPAGCD[6:0] is hex40 which is 0 dB.
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January 22, 2004
AV2722 (Preliminary)
ADDRESS 06, ADC PATH SERIAL OUTPUT PORT CONTROL REGISTER (CREG6[7:0]) CREG6[7:0] A[7:0] BIT7 Hex 06 Default Value
master
BIT6 adhrsc 0
BIT5
adsfdly
BIT4
adinvsc
BIT3
BIT2
BIT1
BIT0
admode[1:0] 0 0
adformat[1:0] 0 0
0
0
0
MASTER: master or slave mode control
0: the chip is operated as "slave". In slave mode, AV2722 accepts SFDA, SFAD, and SC. 1:the chip is operated as "master". In master mode, AV2722 generates SFDA, SFAD and SC. In either mode, DAC and ADC can be operated at different sampling rate.
ADHRSC:ADCs use higher rate SC
0:ADC path uses whatever SC is provided, either master or slave mode (default). 1:ADC path uses higher rate SC. When the DAC path is at higher sampling than the ADC path, program this bit to "1" allows SDO output to shift out data at the higher SC rate.
ADSFDLY: Delay SFAD by 1 SC in the ADC path.
0: do not delay the SF by 1 SC cycle (default). 1: delay the SFAD by 1 SC cycle.
ADINVSC: Invert the SC bit clock.
0: do not invert the SC bit clock (default). 1: invert the SC bit clock.
ADMODE[1:0]: These two bits define the ADC path serial output data mode.
00: left justified mode(defalut). 01: I2S mode. 10: normal mode 11: DSP mode
ADFORMAT[1:0]: These two bits define the audio serial output data bit length.
00: 24 bits (default). 01: 20-bits. 10: 18 bits. 11: 16 bits.
19-29
January 22, 2004
AV2722 (Preliminary)
ADDRESS 07, ADC PATH HIGH PASS FILTER CONTROL REGISTER (CREG7[7:0]) CREG7[7:0] A[7:0] BIT7 Hex 07 Default Value 0 0 0 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1
HPFOSEN
BIT0
HPFEN
Reserved 0 0 0
1
1
HPFOSEN: high-pass filter (HPF) offset enable in the ADC path.
0: allow HPF to use previous stored data. 1: allow HPF to use new coming data. (default)
HPFEN: high-pass filter (HPF) enable in the ADC path.
0: bypass the high-pass filter. 1: enable the high-pass filter (default).
ADDRESS 08, ADC PATH LEFT CHANNEL GAIN AND MUTE CONTROL REGISTER (CREG8[7:0]) CREG8[7:0] A[7:0] BIT7 Hex 08 Default Value
ADCMUTEL
BIT6
BIT5
BIT4
BIT3
BIT2
ADCGAINL[4:0]
BIT1
BIT0
reserved 0 0 1 0
0
0
1
0
ADCMUTEL: ADC left channel mute control.
0: do not mute the ADC left channel (default). 1: mute the ADC left channel, SDO will shift out all zero data in the left channel.
ADCGAINL[4:0]: 5-bit ADC left channel input gain (volume) control. The default value of ADCGAINL[4:0] is binary 10010 which is corresponding to 0 dB.
20-29
January 22, 2004
AV2722 (Preliminary)
ADDRESS 09, ADC PATH RIGHT CHANNEL GAIN AND MUTE CONTROL REGISTER (CREG9[7:0]) CREG9[7:0] A[7:0] BIT7 Hex 09 Default Value
ADCMUTER
BIT6
BIT5
BIT4
BIT3
BIT2
ADCGAINR[4:0]
BIT1
BIT0
reserved 0 0 1 0
0
0
1
0
ADCMUTER: ADC right channel mute control.
0: do not mute the ADC right-channel (default). 1: mute the ADC right channel, SDO will shift out all zero data in the right channel.
ADCGAINR[4:0]: 5-bit ADC rightchannel input gain (volume) control. The default value of ADCGAINR[4:0] is binary 10010 which is corresponding to 0 dB. ADDRESS 0A, ADC POWER DOWN CONTROL REGISTER (CREG10[7:0]) CREG10[7:0] A[7:0] BIT7 Hex 0A Default Value 0 0 BIT6 BIT5 Reserved 0 0 0 BIT4 BIT3 BIT2
ADCLPWDN 1
BIT1
ADCRPWDN
BIT0
PWDNMICBIAS
1
0
ADCLPWDN: ADC left channel power down.
0: do not shut down power of ADC left channel. 1: shut down power of ADC left channel (default)
ADCRPWDN: ADC right channel power down
0: do not shut down power of ADC right channel. 1: shut down power of ADC right channel (default).
PWDNMICBIAS: Microphone bias circuit power down.
0: do not shut down microphone bias circuit (default). 1: shut down power of microphone bias circuit.
ADDRESS 0B, ADC LEFT AND RIGHT MICROPHONE GAIN CONTROL REGISTER (CREG11[7:0]) CREG11[7:0] A[7:0] BIT7 Hex 0B Default Value Reserved 0 BIT6
USEADCL 0
BIT5
BIT4
BIT3 reserved 0
BIT2
USEADCR 0
BIT1
BIT0
MICGAINL[1:0] 0 0
MICGAINR[1:0]
0
0
USEADCL: use ADC microphone left channel.
0: ADC left channel microphone is not used (default). 1: ADC left channel microphone is used.
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January 22, 2004
AV2722 (Preliminary)
By default, ADC microphone left channel is shut down (ADCLPWDN=1). If ADCLPWDN is programmed to "0", this bit must be programmed to "1" to use the left channel microphone
MICGAINL[1:0]:2-bit left channel microphone gain
00: no gain increase (default). 01: 6 dB gain increase for the left channel microphone input. 10: 12 dB gain increase for the left channel microphone input. 11: 18 dB gain increase for the left channel microphone input.
USEADCR: use ADC microphone right channel.
0: ADC left channel microphone is not used (default). 1: ADC right channel microphone is used. By default, ADC microphone right channel is shut down (ADCRPWDN=1). If ADCRPWDN is programmed to "0", this bit must be programmed to "1" to use the right channel microphone.
MICGAINL[1:0]:2-bit right channel microphone gain.
00: no gain increase (default). 01: 6 dB gain increase for the right channel microphone input. 10: 12 dB gain increase for the right channel microphone input. 11: 18 dB gain increase for the right channel microphone input.
ADDRESS 0C, SOFTWARE RESET CONTROL REGISTER (CREG12[7:0]) CREG12[7:0] A[7:0] BIT7 Hex0C Default Value 0 0 0 BIT6 BIT5 BIT4 Reserved 0 0 0 0 BIT3 BIT2 BIT1 BIT0
SOFRST
0
SOFRST: [1:0]: software reset.
0: no software reset. 1: software reset.
DIGITAL INTERPOLATION FILTER CHARACTERISTICS (TO BE INSERTED) DIGITAL FILTER FREQUENCY RESPONSE (TO BE INSERTED)
22-29
January 22, 2004
AV2722 (Preliminary)
CONNECTION EXAMPLE
3.3V 0.1uF 47uF
1 2
VDD SC SDI
VSS 28 XCK 27 RS/ 26 SCL SDA CSB MODE 25 24 23 22
47K 47K
Audio Serial I/O Interface
3
4 SFDA AV2722 5 6 7 8 SDO SFAD HPVR VDDH HOUTL
3-wire interface, MODE is not connected. 2-wire interface, MODE is connected For microphone input, remove 220pF capacitor and 5.6K resistors, short R1
unpop 1uF R1 5.6K
to headphone ground in CAPLESS mode, otherwise, no connect 10uf 0.1uf 10uf
HPDET 21 AINL 20 AINR 19 MICBIAS 18 VCM 17 VSSA 16 VSSA 15
0.1uf
3.3 V or GND
9
47K 220uF 10uf
10 HOUTR 11 VSSH 12 AOUTL
unpop
220pF
5.6K
680 ohm 10uf unpop 1uF 5.6K
47K
220uF
13 AOUTR
unpop
220pF
5.6K
Left channel LPF Right channel LPF
14 VDDA
to microphone
3.3V 0.1uF 47uF
20K 22uF
220pF 10uF
20K 100K 1000pF
20K
Left or Right Channel LPF
23-29
January 22, 2004
AV2722 (Preliminary)
ABSOLUTE MAXIMUM RATINGS
Symbol VDD
VDDA VDDH
Characteristics Power Supply Voltage (Measured to Vss)
Min -0.3
Max +3.6
Units V
Vid Via Vo TA Tstg Tstor Tj Tsol Tvsol Notes:
Digital Input Applied Voltage1 Analog Input Applied Voltage1 Digital Output Voltage Operating Temperature Range Storage Temperature before soldering Storage Temperature after soldering Junction Temperature (Plastic Package) Lead Soldering Temperature (10 sec., 1/4" from pin) Vapor Phase Soldering (1 minute)
GND-0.3 GND-0.3 GND-0.3 -25
VDD+0.3 VDDA+0.3 VDD+0.3 +85 30
o o o o o o
V V V
C C C C C C
-65 -65
+150 +150 240 180
Absolute maximum ratings are limiting values applied individually, while all other parameters are within specified operating conditions.
24-29
January 22, 2004
AV2722 (Preliminary)
RECOMMENDED OPERATING CONDITIONS
Symbol VDD VDDA VDDH Vss VSSA VSSH Ta
Characteristics Power supply voltage
Min
Typical
Max 3.6
Units V
0 Ground Ambient operating temperature range 0 70
V
oC
ELECTRICAL CHRACTERISTICS Parameter Digital Input VIH VIL IIH IIL Digital Input Voltage, Logic HIGH, TTL Compatible Inputs. Digital Input Voltage, Logic LOW, TTL Compatible Inputs Digital Input Current, Logic HIGH, (VIN=4.0V) Digital Input Current, Logic LOW, (VIN=0.4V) 2.0 VSS VDD 0.8 TBD TBD V V
A A
Characteristics / Test Conditions
Min
Typ
Max
Units
Serial Audio Port Timing (Slave Mode)
tsc
SC Pulse Cycle Time SC Pulse Width, HIGH SC Pulse Width, LOW Audio Data Setup Time With Respect To Rising Edge of SC Audio Data Hold Time With Respect to Rising Edge of SC Audio SFSetup Time With Respect To Rising Edge of SC Audio SF Hold Time With Respect To Rising Edge of SC
100 50 50 30 30 30 30
ns ns ns ns ns ns ns
tscH tscL tSU tHD tsfsc tscsf
Serial Audio Port Timing (Master Mode) tmSU tmHD SDI audio data setup time SDI audio data hold time 10 10 ns ns
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January 22, 2004
AV2722 (Preliminary)
Parameter tmsfd tmsdod Characteristics / Test Conditions SFDA/SFAD propagation delay from SC falling edge SDO propagation delay from SC falling edge Min Typ Max 10 10 Units ns ns
Serial Command Port Timing (MPU type Mode) TSCL tSCLH tSCLL tsdasu tsdahd tcsbl tcsbh tsclcsb tcsbscl SCL cycle time SCL high time SCL low time SDA to SCL setup time SCL to SDA hold time CSB pulse low time CSB pulse high time SCL rising edge to CSB rising edge CSB rising edge to SCL rising edge 100 80 40 20 20 20 20 20 20 ns ns ns ns ns ns ns ns ns
Serial Command Port Timing (I2S Mode) fsc tsu;sta thd;sta tsu;sto tLOW tHIGH tr tf tsu;DAT thd;DAT Tvd;DAT tBUF SCL clock frequency START condition setup time START condition hold time STOP condition setup time SCL low time SCL high time SCL and SDA rise time SCL and SDA fall time Data setup time Data hold time SCL low to data output valid Bus free time 4.7 250 0 3.4 4.7 4.0 4.0 4.7 4.0 1.0 0.3 100 KHz
s s s s s s s
ns ns
s s
ADC Line Input Vin(line) Input signal level for line input (0dB) A-weighted, 0 dB gain @fs=48KHz SNR A-weighted, 0 dB gain @fs=96KHz A-weighted, 0 dB gain @fs=48KHz, VDDA=2.7V TBD TBD TBD TBD Vrms dB dB dB
26-29
January 22, 2004
AV2722 (Preliminary)
Parameter THD DR PSRR Characteristics / Test Conditions Total Harmonic Distortion Dynamic Range, A weighted -60 db full scale input Power Supply Rejection Ratio, 1KHz 100 mVpp Power Supply Rejection Ratio, 20 Hz to 20KHz 100 mVpp ADC Channel Separation (@ 1KHz input) Mute Attenuation (0 dB @ 1KHz input) RINLINE CINLINE Input resistance, 0 dB gain Input resistance, 12 dB gain Input Capacitance Min Typ TBD TBD TBD TBD TBD TBD TBD TBD TBD Max Units dB dB dB dB dB dB

pF
ADC Microphone Input @ 0dB gain, fs=48KHz Vin(mic) SNR THD PSRR Input signal level for microphone input (0dB) A weighted, 0 dB gain 0db input, 0 db gain Power Supply Rejection Ratio, 1KHz 100 mVpp Power Supply Rejection Ratio, 20 Hz to 20KHz 100 mVpp Dynamic Range, A weighted, -60 dB full scale input Mute Attenuation (@0dB, 1KHz input) RINMIC CINMIC Input Resistance Input Capacitance TBD TBD TBD TBD TBD TBD TBD TBD TBD Vrms dB dB dB dB dB dB
DR
pF
MICROPHONE BIAS VMICBIAS IMICBIAS Vn Microphone bias voltage Microphone bias current Output Noise Voltage (1K to 20 KHz) TBD TBD TBD V pF nV/Hz1/2
Line Output for DAC Playback (Load =10K , 50pF) Vout 0 db full scale output voltage A-weighted, 0 dB gain @fs=48KHz SNR DR A-weighted, 0 dB gain @fs=96KHz A-weighted, 0 dB gain @fs=48KHz, VDDA=2.7V Dynamic Range, -60 dB full scale input TBD TBD TBD TBD TBD Vrms dB dB dB dB
27-29
January 22, 2004
AV2722 (Preliminary)
Parameter THD Characteristics / Test Conditions Total Harmonic Distortion, 1KHz, 0dBfs Total Harmonic Distortion, 1KHz, -3dBfs Power Supply Rejection Ratio, 1KHz 100 mVpp PSRR Power Supply Rejection Ratio, 20 Hz to 20KHz 100 mVpp Mute Attenuation (1KHz, 0 dB) Stereo Headphone Output Vout Pout SNR 0 dB Full scale output voltage Output power with RL= 32 , Output power with RL= 16 , Signal To Noise Ratio, A-weighted 1KHz, with RL= 32 , Pout =10mW rms (-5dB) THD 1KHz, with RL= 32 Pout = 20 mW rms (-2dB) Power Supply Rejection Ratio, 1KHz 100 mVpp PSRR Power Supply Rejection Ratio, 20 Hz to 20KHz 100 mVpp Mute Attenuation 1KHz, 0 dB TBD TBD TBD TBD TBD TBD TBD TBD TBD Vrms mW mW dB % dB % dB dB dB dB TBD TBD dB dB Min Typ TBD TBD TBD Max Units dB dB dB
Test Conditions: VDD, VDDH, VDDA= 3.3 V, VSS=0 V, TA25 oC, slave mode, 48 KHz sampling rate, 256 fs.
28-29
January 22, 2004
AV2722 (Preliminary)
PACKAGING INFORMATION
28 PIN SSOP (10.2 x 5.3 x 1.75 MM)
b 28 e 15
E1
GAUGE PLANE
E
c
L 1 D 14 L1
0.25
A A2
-c-
A1
0.10
SEATING PLANE
SYMBOLS MIN A A1 A2 b c D E e E1 L L1 REF: 0o 5.00 0.55 ----0.05 1.65 0.22 0.09 9.90 7.40
DIMENSIONS (mm) NOM ----0.13 1.75 --------10.20 7.80 0.65 BSC 5.30 0.75 1.25 REF 4o 8o 5.60 0.95 MAX 2.0 0.25 1.85 0.38 0.25 10.50 8.20
JEDEC.95, MO-150
29-29
January 22, 2004

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